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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z86C02/E02/L02
LOW-COST, 512-BYTE ROM MICROCONTROLLERS
FEATURES
Device Z86C02 Z86E02 Z86L02 ROM (KB) 512 512 512 RAM* Speed Auto Permanent (Bytes) (MHz) Latch WDT 61 61 61 8 8 8 Optional Optional Optional Optional Optional Optional
s
1
Note: *General-Purpose s s
ROM Mask/OTP Options: - Low-Noise (Z86C02/E02 only) - ROM Protect - Auto Latch - Permanent Watch-Dog Timer (WDT) - RC Oscillator (Z86C02/L02 Only) - 32 KHz Operation (Z86C02/L02 Only) One Programmable 8-Bit Counter/Timer with a 6-Bit Programmable Prescaler Power-On Reset (POR) Timer On-Chip Oscillator that Accepts RC, Crystal, Ceramic Resonator, LC, or External Clock Drive (C02/L02 only) On-Chip Oscillator that Accepts RC or External Clock Drive (Z86E02 SL1903 only) On-Chip Oscillator that Accepts Crystal, Ceramic Resonator, LC, or External Clock Drive (Z86E02 only) Clock-Free WDT Reset Low-Power Consumption (50mw) Fast Instruction Pointer (1.5s @ 8 MHz) Fourteen Digital Inputs at CMOS Levels; Schmitt-Triggered
18-Pin DIP and SOIC Packages
s
0C to 70C Standard Temperature -40C to 105C Extended Temperature (Z86C02/E02 only) 3.0V to 5.5V Operating Range (Z86C02) 4.5V to 5.5V Operating Range (Z86E02) 2.0V to 3.9V Operating Range (Z86L02) 14 Input / Output Lines Five Vectored, Prioritized Interrupts from Five Different Sources Two On-Board Comparators Software Enabled Watch-Dog Timer (WDT) Programmable Interrupt Polarity Two Standby Modes: STOP and HALT Low-Voltage Protection
s s
s
s
s s
s
s s s s s
s s s s
GENERAL DESCRIPTION
Zilog's Z86C02/E02/L02 microcontrollers (MCUs) are members of the Z8(R) single-chip MCU family, which offer easy software/hardware system expansion. For applications demanding powerful I/O capabilities, the MCU's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. One on-chip counter/timer, with a large number of user-selectable modes, off-load the system of administering realtime tasks such as counting/timing and I/O data communi-
DS96DZ80301 (11/96)
PRELIMINARY
1-1
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
GENERAL DESCRIPTION (Continued)
cations. Additionally, two on-board comparators process analog signals with a common reference voltage (Figure 1). Note: All Signals with a preceding front slash, "/", are active Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Input Vcc GND
Power connections follow conventional descriptions below: Connection Power Ground
XTAL
Circuit VCC GND
Device VDD VSS
Port 3
Machine Timing & Inst. Control
Counter/ Timer
ALU
Interrupt Control
FLAG
Program Memory
Two Analog Comparators
Register Pointer General-Purpose Register File
Program Counter
Port 2
Port 0
I/O (Bit Programmable)
I/O
Figure 1. Z86C02/E02/L02 Functional Block Diagram
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PRELIMINARY
DS96DZ80301 (11/96)
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
GENERAL DESCRIPTION (Continued)
D7-D0 Z8 MCU A10-A0 Address Counter A10-A0 3 Bits PGM Mode Logic Option Bits D7-D0 Address MUX
A10-A0 Data MUX Z8 PORT2 /OE P31
EPROM D7-D0
Clear Clock P00 P01
EPM /CE /PGM P32 XT1 P02
VPP P33
Figure 2. EPROM Programming Mode Block Diagram
PIN DESCRIPTIONS
Table 1. 18-Pin Standard Mode Identification
P24 P25 P26 P27 Vcc XTAL2 XTAL1 P31 P32 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P23 P22 P21 P20 GND P02 P01 P00 P33
Pin # 1-4 5 6 7 8 9 10 11-13 14 15-18
Symbol
Function
Direction In/Output Output Input Input Input Input In/Output In/Output
P24-P27 Port 2, Pins 4, 5, 6, 7 VCC Power Supply Crystal Oscillator Clock XTAL1 Crystal Oscillator Clock P31 Port 3, Pin 1, AN1 P32 Port 3, Pin 2, AN2 P33 Port 3, Pin 3, REF P00-P02 Port 0, Pins 0, 1, 2 GND Ground P20-P23 Port 2, Pins 0, 1, 2, 3 XTAL2
Standard Mode
Figure 3. 18-Pin Standard Mode Configuration
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PRELIMINARY
DS96DZ80301 (11/96)
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
D4 D5 D6 D7 Vcc N/C /CE /OE EPM D3 D2 D1 D0 GND /PGM CLOCK CLEAR VPP
P24 P25 P26 P27 VCC XTAL2 XTAL1 P31 P32 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 P23 P22 P21 P20 GND P02 P01 P00 P33
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
1
EPROM Mode
Figure 4. 18-Pin EPROM Mode Configuration Table 2. 18-Pin EPROM Mode Identification Pin # 1-4 5 6 7 8 9 10 11 12 13 14 15-18 Symbol D4-D7 Vcc NC /CE /OE EPM VPP Clear Clock /PGM GND D0-D3 Function Data 4, 5, 6, 7 Power Supply No Connection Chip Enable Output Enable EPROM Program Mode Program Voltage Clear Clock Address Program Mode Ground Data 0, 1, 2, 3 Direction In/Output Pin # 1-4 Input Input Input Input Input Input Input In/Output 5 6 7 8 9 10 11-13 14 15-18
Figure 5. 18-Pin SOIC Configuration Table 3. 18-Pin SOIC Pin Identification Standard Mode Symbol P24-P27 Vcc XTAL2 XTAL1 P31 P32 P33 P00-P02 GND P20-P23 Function Port 2, Pins 4,5,6,7 Power Supply Crystal Osc. Clock Crystal Osc. Clock Port 3, Pin 1, AN1 Port 3, Pin 2, AN2 Port 3, Pin 3, REF Port 0, Pins 0,1,2 Ground Port 2, Pins 0,1,2,3 Direction In/Output
Output Input Input Input Input In/Output In/Output
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PRELIMINARY
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS [Note 1] Voltage on VDD Pin with Respect to VSS Voltage on Pin 7 with Respect to VSS [Note 2] (Z86C02/L02) Voltage on Pin 7,8,9,10 with Respect to VSS [Note 2] (Z86E02) Total Power Dissipation Maximum Allowed Current out of VSS Maximum Allowed Current into VDD Maximum Allowed Current into an Input Pin [Note 3] Maximum Allowed Current into an Open-Drain Pin [Note 4] Maximum Allowed Output Current Sinked by Any I/O Pin Maximum Allowed Output Current Sourced by Any I/O Pin Maximum Allowed Output Current Sinked by Port 2, Port 0 Maximum Allowed Output Current Sourced by Port 2, Port 0 Notes: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power dissipation should not exceed 462 mW for the package. Power dissipation is calculated as follows: Total Power dissipation = VDD x [IDD - (sum of IOH)] + sum of [(VDD - VOH) x IOH] + sum of (V0L x I0L) Min -40 -65 -0.7 -0.3 -0.7 -0.7 Max +105 +150 +12 +7 VDD+1 VDD+1 462 300 270 +600 +600 20 20 80 80 Units C C V V V V mW mA mA A A mA mA mA mA
1
-600 -600
1. This applies to all pins except where otherwise noted. 2. Maximum current into pin must be 600A. There is no input protection diode from pin to VDD. 3. This excludes Pin 6 and Pin 7. 4. Device pin is not at an output Low state.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 6).
From Output Under Test
150 pF
Figure 6. Test Load Diagram
CAPACITANCE
TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND. Parameter Input capacitance Output capacitance I/O capacitance DS96DZ80301 (11/96) Min 0 0 0 Max 15 pF 20 pF 25 pF PRELIMINARY 1-5
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
DC ELECTRICAL CHARACTERISTICS Z86C02
TA = 40C to +105C TA = 0C to +70C Sym. VCH Parameter Clock Input High Voltage VCC [4] 3.0V 5.5V VCL Clock Input Low Voltage 3.0V 5.5V VIH VIL VOH Input High Voltage Input Low Voltage Output High Voltage 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V VOL1 Output Low Voltage 3.0V 5.5V 3.0V 5.5V VOL2 Output Low Voltage 3.0V 5.5V VOFFSET Comparator Input Offset Voltage VLV VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range 3.0V 5.5V 3.0V 5.5V VVICR 3.0V 5.5V 2.2 2.0 -1.0 -1.0 -1.0 -1.0 VSS-0.3 VSS-0.3 Min 0.8 VCC 0.8 VCC VSS-0.3 VSS-0.3 0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 0.8 0.4 0.8 0.4 1.0 0.8 25 25 2.8 3.0 1.0 1.0 1.0 1.0 VCC -1.0 VCC -1.5 Max VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
Typical @ 25C 1.7 2.8 0.8 1.7 1.8 2.8 0.8 1.5 3.0 4.8 3.0 4.8 0.2 0.1 0.2 0.1 0.8 0.3 10 10 2.6 2.6 Units V V V V V V V V V V V V V V V V V V mV mV V V V A A A A V V IOH = -2.0 mA IOH = -2.0 mA Low Noise @ IOH = -0.5 mA Low Noise @ IOH = -0.5 mA IOL = +4.0 mA IOL = +4.0 mA Low Noise @ IOL = 1.0 mA Low Noise @ IOL = 1.0 mA IOL = +12 mA IOL = +12 mA [5] [5] [5] [5] Conditions Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator [1] [1] [1] [1] [5] [5] Notes
[9] [10] VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC [9] [10]
IIL
IOL
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PRELIMINARY
DS96DZ80301 (11/96)
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
DC CHARACTERISTICS Z86C02
TA = 40C to+105C TA = 0C to +70C Typical VCC [4] Min Max @ 25C Units 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 3.0V 5.5V 5.5V 3.0V 5.5V IALH Auto Latch High Current 3.0V 5.5V 3.5 7.0 8.0 11.0 2.5 4.0 4.0 5.0 3.5 7.0 5.8 9.0 8.0 11.0 2.5 4.0 3.0 4.5 4.0 5.0 10 20 10 20 12 32 -8 -16 1.5 3.8 3.0 4.4 0.7 2.5 1.0 3.0 1.5 3.8 2.5 4.0 3.0 4.4 0.7 2.5 0.9 2.8 1.0 3.0 1.0 1.0 1.0 1.0 3.0 16 -1.5 -8.0 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A
1
Conditions @ 2 MHz @ 2 MHz @ 8 MHz @ 8 MHz @ 2 MHz @ 2 MHz @ 8 MHz @ 8 MHz @ 1 MHz @ 1 MHz @ 2 MHz @ 2 MHz @ 4 MHz @ 4 MHz @ 1 MHz @ 1 MHz @ 2 MHz @ 2 MHz @ 4 MHz @ 4 MHz Notes [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [6,7,8] [6,7,8] [6,7,8] [6,7,8] [6,7,8] [6,7,8] [6,7,8,9] [6,7,8,10] [6,7,8,9] [6,7,8,10]
Sym. Parameter ICC Supply Current
ICC1 Standby Current (Halt Mode)
ICC Supply Current (Low Noise Mode)
ICC1 Standby Current (Low Noise Halt Mode)
ICC2 Standby Current (Stop Mode)
IALL
Auto Latch Low Current
0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC
Notes: 1. ort 0, 2, and 3 only. 2. VSS = 0V = GND. 3. The device operates down to VLV The minimum operational VCC is determined on the value of the voltage VLV at the ambient temperature. 4. VCC = 3.0V to 5.5V, typical values measured at VCC = 3.3V and VCC = 5.0V. 5. Standard mode (not Low EMI mode). 6. Inputs at VCC or VSS, outputs unloaded. 7. Halt mode and Low EMI mode. 8. WDT not running. 9. TA= 0C to 70C. 10. TA= 40C to 105C.
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PRELIMINARY
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
DC CHARACTERISTICS Z86L02
VCC [4] 2.0V 3.9V VCL Clock Input Low Voltage 2.0V 3.9V VIH VIL VOH VOL1 VOL2 VOFFSET VLV IIL Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Comparator Input Offset Voltage VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 1.4 2.0V 3.9V 2.0V 3.9V VVICR Comparator Input Common Mode Voltage Range -1.0 -1.0 -1.0 -1.0 VSS -0.3 TA = 0C to +70C Min Max 0.9 VCC VCC+0.3 0.9 VCC VSS-0.3 VSS-0.3 0.9 VCC 0.9 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 0.8 0.4 1.0 0.8 25 25 2.15 1.0 1.0 1.0 1.0 VCC -1.0 VCC+0.3 0.1 VCC 0.1 VCC VCC+0.3 VCC+0.3 0.1 VCC 0.1 VCC 3.0 3.0 0.2 0.1 0.8 0.3 10 10 Typical @ 25C
Sym. VCH
Parameter Clock Input High Voltage
Units Conditions V Driven by External Clock Generator V Driven by External Clock Generator V Driven by External Clock Generator V Driven by External Clock Generator V V V V V V V V V V mV mV V A A A A V VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC IOH = - 500 A IOH = -500 A IOL = +1.0 mA IOL = +1.0 mA IOL = + 3.0 mA IOL = + 3.0 mA
Notes
[1] [1] [1] [1] [5] [5] [5] [5] [5] [5]
IOL
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PRELIMINARY
DS96DZ80301 (11/96)
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers TA = 0C to +70C Typical Min Max @ 25C 3.3 6.8 6.0 9.0 2.3 3.8 3.8 4.8 10 10 12 32 -8 -16
Sym Parameter ICC Supply Current
VCC [4] 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V 2.0V 3.9V
Units mA mA mA mA mA mA mA mA A A A A A A
Conditions @ 2 MHz @ 2 MHz @ 8 MHz @ 8 MHz @ 2 MHz @ 2 MHz @ 8 MHz @ 8 MHz
Notes [5,6] [5,6] [5,6] [5,6] [5,6,7] [5,6,7] [5,6,7] [5,6,7] [6,7] [6,7]
1
ICC1 Standby Current (Halt Mode)
ICC2 Standby Current (Stop Mode) IALL Auto Latch Low Current
1.0 1.0 3.0 16 -1.5 -8.0
0V < VIN < VCC 0V < VIN < VCC 0V < VIN < VCC
IALH Auto Latch High Current
Notes: 1. Port 0, 2, and 3 only 2. VSS = 0V = GND.The device operates down to VLV. The minimum operational VCC is determined by the value of the voltage VLV at the ambient temperature. 3. VCC = 2.0V to 3.9V, typical values measured at VCC = 3.3 V. 4. Standard Mode (not Low EMI mode). 5. Inputs at VCC or VSS, outputs are unloaded. 6. WDT is not running.
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PRELIMINARY
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
DC CHARACTERISTICS Z86E02
TA = -40C to +105C TA = 0C to +70C Min Max 0.8 VCC 0.8 VCC VSS-0.3 VSS-0.3 0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4 VCC-0.4 VCC-0.4 0.4 0.4 0.4 0.4 1.0 1.0 25 25 3.3 3.6 1.0 1.0 1.0 1.0 VCC -1.0 VCC -1.5 VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
Sym. VCH
Parameter Clock Input High Voltage
VCC [4] 4.5V 5.5V
Typical @ 25C 2.8 2.8 1.7 1.7 2.8 2.8 1.5 1.5 4.8 4.8 4.8 4.8 0.1 0.1 0.1 0.1 0.8 0.8 10 10 3.0 3.0
Units V V V V V V V V V V V V V V V V V V mV mV V V A A A A V V
Conditions Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
VCL
Clock Input Low Voltage
4.5V 5.5V
VIH VIL VOH
Input High Voltage Input Low Voltage Output High Voltage
4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V
IOH = -2.0 mA IOH = -2.0 mA Low Noise @ IOH = -0.5 mA IOL = +4.0 mA IOL = +4.0 mA Low Noise @ IOL = 1.0 mA Low Noise @ IOL = 1.0 mA IOL = +12 mA IOL = +12 mA
[5] [5]
VOL1
Output Low Voltage
4.5V 5.5V 4.5V 5.5V
[5] [5]
VOL2 VOFFSET VLV IIL
Output Low Voltage Comparator Input Offset Voltage VCC Low Voltage Auto Reset Input Leakage (Input Bias Current of Comparator) Output Leakage Comparator Input Common Mode Voltage Range
4.5V 5.5V 4.5V 5.5V 2.6 2.2 -1.0 -1.0 -1.0 -1.0 VSS-0.3 VSS-0.3
[5] [5]
[9] [10] VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC [9] [10]
4.5V 5.5V 4.5V 5.5V
IOL VVICR
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PRELIMINARY
DS96DZ80301 (11/96)
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers TA = -40C to +105C TA = 0C to +70C Sym. Parameter ICC Supply Current VCC [4] 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 4.5V 5.5V 5.5V 4.5V 5.5V
ALH
Typical @ 25C 3.8 3.8 4.4 4.4 2.5 2.5 3.0 3.0 3.8 3.8 4.0 4.0 4.4 4.4 2.5 2.5 2.7 2.7 3.0 3.0 1.0 1.0 1.0 1.0 16 16 -8.0 -8.0 Units mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA A A A A A A A A Conditions @ 2 MHz @ 2 MHz @ 8 MHz @ 1 MHz @ 2 MHz @ 2 MHz @ 4 MHz @ 4 MHz Notes [5,6] [5,6] [5,6] [5,6] [5,6] [5,6] [5,6] [5,6] [6] [6] [6] [6] [6] [6] [6,7,8] [6,7,8] [6,7,8] [6,7,8] [6,7,8] [6,7,8] [6,7,9] [6,7,10] [6,7,9] 6,7,10]
Min
ICC1 Standby Current (HALT mode)
ICC Supply Current (Low Noise Mode)
ICC1 Standby Current (Low Noise Halt Mode)
ICC2 Standby Current (Stop Mode)
IALL Auto Latch Low Current Auto Latch High
Max 9.0 9.0 15.0 15.0 4.0 4.0 5.0 5.0 9.0 9.0 11.0 11.0 15.0 15.0 4.0 4.0 4.5 4.5 5.0 5.0 10 20 10 20 32 32 -16 -16
1
@ 2 MHz @ 2 MHz @ 4 MHz @ 4 MHz @ 1 MHz @ 1 MHz @ 2 MHz @ 2 MHz @ 4 MHz @ 4 MHz
0V 4.5V 5.5V
Notes: 1. Port 0, 2, and 3 only. 2. VSS = 0V = GND. 3. The device operates down to VLV of the specified frequency for VLV. The minimum operational VCC is determined by the value of the voltage VLV at the ambient temperature. 4. The VLV increases as the temperature decreases. 5. VCC = 4.5V to 5.5V, typical values measured at VCC = 5.0V. 6. Standard mode (not Low EMI mode). 7. Inputs at VCC or VSS, outputs unloaded. 8. WDT not running. 9. Halt mode and Low EMI mode. 10. TA= 0C to 70C.TA= -40C to 105C.
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
AC ELECTRICAL CHARACTERISTICS
1
3
Clock
2 7 7 2 3
T
IN
4 6 5
IRQ
N
8 9
Figure 7. AC Electrical Timing Diagram
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
TA = -40C to +105C TA= 0C to +70C 8 MHz No. 1 2 3 4 5 6 7 8 9 10 Symbol TpC TrC,TfC TwC TwTinL TwTinH TpTin TrTin, TtTin TwIL TwIH Twdt Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Time Int. Request Input Low Time Int. Request Input High Time Watch-Dog Timer Delay Time Before Time-Out VCC 2.0V 5.5V 2.0V 5.5V 2.0V 5.5V 2.0V 5.5V 2.0V 5.5V 2.0V 5.5V 2.0V 5.5V 2.0V 5.5V 3.0V 5.5V 2.0V 3.0V 5.5V 2.0V 3.0V 5.5V 2.0V 3.0V 5.5V Min 125 125 Max DC DC 25 25 Units ns ns ns ns ns ns ns ns Notes [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1,2,3] [1,2,3] [1,2,3] [1,2,3]
1
62 62 70 70 5TpC 5TpC 8TpC 8TpC 100 100 70 70 5TpC 5TpC 25 10 5 70 50 10 8 4 2
ns ns ns ns
11
Tpor
Power-On Reset Time
250 150 70 76 38 18
ms ms ms ms ms ms ms ms ms
[4] [4] [4] [5] [5] [5]
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. IRQ 0,1,2 only. 4. Z86E02 only. 5. Z86C02/L02 only.
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
AC ELECTRICAL CHARACTERISTICS Low Noise Mode (Z86C02/E02 Only)
TA = -40C to +105C TA= 0C to +70C 1 MHz 4 MHz Min Max Min Max 1000 1000 DC DC 25 25 250 250 DC DC 25 25
No.
Symbol
Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Timer Input Low Width Timer Input High Width Timer Input Period Timer Input Rise and Fall Time Int. Request Input Low Time Int. Request Input High Time Power-On Reset Time
VCC 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 2.0V 3.0V 5.5V 3.0V 5.5V
Units ns ns ns ns ns ns ns ns
Notes [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1,2,3] [1,2,3] [1,2,3] [1,2,3] [4] [4] [5] [5] [5]
1 TPC 2 TrC TfC 3 TwC 4. TwTinL 5 TwTinH 6 TpTin 7 TrTin, TtTin 8 TwIL 9 TwIH 10 Tpor
500 500 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 50 10 8 4 2 10 5
125 125 70 70 2.5TpC 2.5TpC 4TpC 4TpC 100 100 70 70 2.5TpC 2.5TpC 50 10 8 4 2 10 5
ns ns ns ns
150 70 76 38 18
150 70 76 38 18
11 Twdt
Watch-Dog Timer Delay
ms ms ms ms ms ms ms
Notes: 1. Timing Reference uses 0.7 VCC for a logic 1 and 0.2 VCC for a logic 0. 2. Interrupt request through Port 3 (P33-P31). 3. IRQ 0,1,2 only. 4. Z86E02 only. 5. Z86C02/L02 only.
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
LOW NOISE VERSION Low EMI Emission
The Z8 can be programmed to operate in a Low EMI emission mode by means of a mask ROM bit option (Z86C02) or OTP bit option (Z86E02). Use of this feature results in:
s s s s
Output drivers have resistances of 200 ohms (typical).
1
All pre-driver slew rates reduced to 10 ns typical. Internal SCLK/TCLK operation limited to a maximum of 4 MHz - 250 ns cycle time.
Oscillator divide-by-two circuitry eliminated. The Low EMI mode is mask-programmable to be selected by the customer at the time the ROM Code is submitted (for Z86C02 only).
PRECAUTION
Stack pointer register (SPL) at FFHex and general purpose register at FEHex are set to 00Hex after reset.
PIN FUNCTIONS OTP Programming Mode
D7-D0 Data Bus. Data can be read from, or written to the EPROM through this data bus. VCC Power Supply. It is 5V during EPROM Read Mode and 6.4V during the other modes (Program, Program Verify, etc.). /CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. /OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input. This pin must toggle for each data output read. EPM EPROM Program Mode. This pin controls the different EPROM Program Modes by applying different voltages. VPP Program Voltage. This pin supplies the program voltage. Clear Clear (active High). This pin resets the internal address counter at the High Level. Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle. /PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus.
Application Precaution
The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above VCC occur on the XTAL1 pin. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the VPP, /CE, /EPM, /OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP mode include the following:
s s
Using a clamping diode to VCC. Adding a capacitor to the affected pin.
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
PIN FUNCTIONS (Continued)
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input and output, respectively). These pins connect a parallelresonant crystal, LC, RC, or an external single-phase clock (8 MHz max) to the on-chip clock oscillator and buffer. Port 0, P02-P00. Port 0 is a 3-bit bi-directional, Schmitttriggered CMOS compatible I/O port. These three I/O lines can be globally configured under software control to be inputs or outputs (Figure 8). Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of 0 or 1. Default condition is Auto Latches enabled.
Z8
Port 0 (I/O)
Open
PAD
Out 1.5 In 2.3 Hysteresis VCC @ 5.0V
Auto Latch Option
R
500 k
Figure 8. Port 0 Configuration
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers Port 2, P27-P20. Port 2 is an 8-bit, bit programmable, bidirectional, Schmitt-triggered CMOS compatible I/O port. These eight I/O lines can be configured under software control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 9).
1
Z8 Port 2 (I/O)
Port 2
Open-Drain Open PAD
Out 1.5 In 2.3 Hysteresis
VCC @ 5.0V
Auto Latch Option R 500 k
Figure 9. Port 2 Configuration
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
PIN FUNCTIONS (Continued)
Port 3, P33-P31. Port 3 is a 3-bit, CMOS compatible port with three fixed input (P33-P31) lines. These three input lines can be configured under software control as digital Schmitt-trigger inputs or analog inputs. These three input lines are also used as the interrupt sources IRQ0-IRQ3 and as the timer input signal TIN (Figure 10).
Z8 Port 3
R247 = P3M
0 = Digital 1 = Analog D1
TIN
DIG. PAD P31 (AN1)
P31 Data Latch IRQ2
+
AN.
IRQ3
PAD P32 (AN2) PAD
P32 Data Latch + P33 (REF)
IRQ0
P33 Data Latch Vcc IRQ1
IRQ 0,1,2 = Falling Edge Detection IRQ3 = Rising Edge Detection
Figure 10. Port 3 Configuration
Comparator Inputs. Two analog comparators are added to input of Port 3, P31 and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In analog mode, P33 input functions serve as a reference voltage to the comparators. The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP mode. The common voltage range is 0-4 V when the VCC
is 5.0 V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output. The comparator output is used for interrupt generation, Port 3 data inputs, or TIN through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input.
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated into the Z86C02/E02/L02 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility. RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for TPOR ms, plus 18 clock cycles, then starts program execution at address 000C (Hex) (Figure 11). The control registers' reset value is shown in Table 4.
XTAL OSC
1
INT OSC POR (Cold Start) Delay Line TPOR ms P27 (Stop Mode)
18 CLK Reset Filter
Chip Reset
Figure 11. Internal Reset Configuration
Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions:
s s s s s
operate in STOP Mode, but it can operate in HALT Mode by using a WDH instruction. Table 4. Control Register Reset Condition Addr Reg. FF FE FD FC FB FA SPL GPR RP FLAGS IMR IRQ D7 D6 D5 D4 D3 D2 D1 D0 Comments 00000000 00000000 00000000 UUUUUUUU 0UUUUUUU U U 0 0 0 0 0 0 IRQ3 is used for positive edge detection UUUUUUUU UUU0UU01 U U U U U U 0 0 P2 open-drain 1 1 1 1 1 1 1 1 Inputs after reset UUUUUU00 UUUUUUUU 00000000
Power bad to power good status Stop-Mode Recovery WDT time-out WDH time-out (in Halt Mode) WDT time-out (in Stop Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator. If the permanent WDT option is selected then the WDT is enabled after reset and operates in RUN Mode, HALT mode, STOP mode and cannot be disabled. If the permanent WDT option is not selected then the WDT, when enabled by the user's software, does not
F9 F8 F7* F6*
IPR P01M P3M P2M
F3 PRE1 F2 T1 F1 TMR Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.
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FUNCTIONAL DESCRIPTION (Continued)
Program Memory. The Z8 addresses up to 512 bytes of internal program memory (Figure 12). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0-511 are on-chip onetime programmable ROM.
1024 Location of First Byte of Instruction Executed After RESET On-Chip ROM 12 11 10 9 8 Interrupt Vector (Lower Byte) 7 6 5 Interrupt Vector (Upper Byte) 4 3 2 1 0 IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2
240 Location 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 Stack Pointer (Bits 7-0) Reserved Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0-1 Mode Port 3 Mode Port 2 Mode T Prescaler o Timer/Counter0 T1 Prescaler Timer/Counter1 Timer Mode Not Implemented RP Flags IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR Indentifiers SPL
IRQ2 IRQ1 IRQ1
128 127 General Purpose Registers 4 3 Port 3 Port 2 Reserved Port 0 P3 P2 P1 P0
IRQ0 IRQ0
2 1
Figure 12. Program Memory Map Register File. The Register File consists of three I/O port registers, 61 general-purpose registers, and 12 control and status registers R0-R3, R4-R127 and R241-R255, respectively (Figure 13). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8. The instructions can access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer (Figure 14) addresses the starting location of the active working-register group.
0
Figure 13. Register File
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register. But is set to 00Hex after any reset. Counter/Timer. There is an 8-bit programmable counter/timers (T1), each driven by its 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources. (Figure 15). The 6-bit prescaler divide the input frequency of the clock source by any integer number from 1 to 64. The prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ5 (T1) is generated.
Specified Working Register Group The lower nibble of the register file address provided by the instruction points to the specified register.
r7 r6
r5 r4
r3 r2
r1 r0
R253 (Register Pointer)
1
The upper nibble of the register file address provided by the register pointer specifies the active working-register group.
FF
Register Group F
F0
R15 to R0
7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 1F
The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode). The counter, but not the prescaler, is read at any time without disturbing its value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock.
Register Group 1
10 0F
R15 to R0 R15 to R4 R3 to R0
Register Group 0 I/O Ports
00
Figure 14. Register Pointer Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 60 general-purpose registers. It is set to 00Hex after any reset.
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Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
FUNCTIONAL DESCRIPTION (Continued)
OSC
/2
*
Internal Clock External Clock Clock Logic /4 6-Bit Down Counter 8-Bit Down Counter IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
T1 Initial Value Register Read
T1 Current Value Register
TIN P31
Internal Data Bus
Figure 15. Counter/Timers Block Diagram
Interrupts. The Z8 has five interrupts from four different sources. These interrupts are maskable and prioritized (Figure 16). The sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and one counter/timer. The Interrupt Mask Register globally or individually enables or disables the five interrupt requests (Table 5). When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are vectored through locations in program memory. When an Interrupt machine cycle is activated, an Interrupt Request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICEBOXTM emulator. The rising edge interrupt is not directly supported on the Z86CCP00ZEM emulator. Table 5. Interrupt Types, Sources, and Vectors Vector Name Source Location IRQ0 AN2(P32) 0,1 IRQ1 REF(P33) 2,3 IRQ2 AN1(P31) 4,5 IRQ3 AN2(P32) 6,7 IRQ4 Reserved 8,9 IRQ5 T1 10,11 Notes: F = Falling edge triggered R = Rising edge triggered
Comments External (F)Edge External (F)Edge External (F)Edge External (R)Edge Reserved Internal
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IRQ0 - IRQ5
1
IRQ
IMR 5 IPR
Global Interrupt Enable Interrupt Request
Priority Logic
Vector Select
Figure 16. Interrupt Block Diagram
Clock. The Z8 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, 8 MHz max, with a series resistance (RS) of less than or equal to 100 Ohms.
The crystal or ceramic resonator should be connected across XTAL1 and XTAL2 using the vendors crystal or ceramic resonator recommended capacitors from each pin directly to device ground pin 14 (Figure 17). Note that the crystal capacitor loads should be connected to VSS, Pin 14 to reduce Ground noise injection.
XTAL1 C1 C1
XTAL1
XTAL1 C R
XTAL1
*
XTAL2 C2
Vss *
*
C2
Vss *
L
Vss *
XTAL2
XTAL2
XTAL2
Ceramic Resonator or Crystal
LC Clock
External Clock
RC Clock
* =Device Ground Pin
Figure 17. Oscillator Configuration
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FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timer and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt service routine, the program continues from the instruction after the HALT. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 A. The STOP mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP mode. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP mode, the I/O port mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP mode, use the following instruction: LD NOP STOP P2M, #1XXX XXXXB Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every TWDT; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of TPOR, plus 18 XTAL clock cycles.The WDT does not run in stop mode, unless the permanent WDT enable option is selected. The WDT does not run in halt mode unless WDH instruction is executed or permanent WDT enable option is selected. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT mode. A WDH instruction executed without executing WDT (5FH) has no effect. Note: Opcode WDH and permanently enabled WDT is not directly supported by the Z86CCP00ZEM. Auto Reset Voltage (VLV). The Z8 has an auto-reset builtin. The auto-reset circuit resets the Z8 when it detects the VCC below VLV. Figure 18 shows the Auto Reset Voltage versus temperature.
Notes: X = Dependent on user's application. Stop-Mode Recovery pin P27 is not edge triggered.
In order to enter STOP or HALT mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, i.e.: FF 6F or FF 7F NOP STOP NOP HALT ; clear the pipeline ; enter STOP mode ; clear the pipeline ; enter HALT mode
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Vcc (Volts) 3.2 3.1 3.0 2.9
Z86E02
1
2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 -40C -20C 0C 20C 40C 60C 80C 100C Temp
Z86L02 Z86C02
Figure 18. Typical Auto Reset Voltage (VLV) vs. Temperature
Options
The Z86C02/E02/L02 offers ROM protect, Low Noise, Auto Latch Disable, RC Oscillator, and Permanent WDT enable features as options. The Z86E02 must be power cycled to fully implement the selected option after programming. Low Noise. The Z8 can operate in a low EMI emission mode by selecting the low noise option. Use of this feature will result in:
s s
EPROM/TEST MODE Disable. When selected, this bit will permanently disable EPROM and Factory Test mode. Auto Latch Disable. Auto Latch Disable option when Selected will globally disable all Auto Latches. RC. RC Oscillator option when selected will allow using a resistor (R) and a capacitor (C) as a clock source. WDT Enable. WDT Enable option bit when selected will have the WDT permanently enabled in all modes and can not be stopped in HALT or STOP Mode. EPROM Mode Description. In addition to VDD and GND (VSS), the Z8 changes all its pin functions in the EPROM mode. XTAL2 has no function, XTAL1 functions as /CE, P31 functions as /OE, P32 functions as EPM, P33 functions as VPP, and P02 functions as /PGM. Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to VCC through a diode to VCC to prevent accidentally entering the OTP mode. The VPP requires both a diode and a 100 pF capacitor. User Modes. Table 6 shows the programming voltage of each mode of Z86E02.
All drivers slew rates are reduced to 10 ns (typical). Internal SCLK/TCLK = XTAL operation is limited to a maximum of 4 MHz - 250 ns cycle time. Output drivers have resistances of 200 ohms (typical). Oscillator divide-by-two circuitry is eliminated.
s s
ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported. (However, instructions LDE and LDEI are not supported.)
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FUNCTIONAL DESCRIPTION (Continued)
Table 6. EPROM Programming Table Programming Modes EPROM READ PROGRAM PROGRAM VERIFY ROM PROTECT LOW NOISE SELECT AUTO LATCH DISABLE WDT ENABLE VPP NU VH VH VH VH VH VH EPM VH VIH VIH VH VIH VIH VIL /CE VIL VIL VIL VH VH VH VH /OE VIL VIH VIL VIH VIH VIL VIH VIL /PGM VIH VIL VIH VIL VIL VIL VIL VIL ADDR ADDR ADDR ADDR NU NU NU NU NU DATA Out In Out NU NU NU NU NU VCC* 5.0V 6.4V 6.4V 5.0-6.4V 5.0-6.4V 5.0-6.4V 5.0-6.4V 5.0-6.4V
EPROM/TEST VH VIL VH MODE Disable Notes: VH=13.0V 0.25 VDC. VIH=As per specific Z8 DC specification. VIL=As per specific Z8 DC specification. X=Not used, but must be set to VH, VIH, or VIL level. NU=Not used, but must be set to either VIH or VIL level. IPP during programming = 40 mA maximum. ICC during programming, verify, or read = 40 mA maximum. * VCC has a tolerance of 0.25V. Internal Address Counter. The address of Z86E02 is generated internally with a counter clocked through pin P01 (Clock). Each clock signal increases the address by one and the "high" level of pin P00 (Clear) will reset the address to zero. Figure 19 shows the setup time of the serial address input.
Programming Waveform. Figures 20, 21, 22, and 23 show the programming waveforms of each mode. Table 7 shows the timing of programming waveforms. Programming Algorithm. Figure 24 shows the flow chart of the Z86E02 programming algorithm.
Table 7. Z86E02 Timing of Programming Waveforms Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name Address Setup Time Data Setup Time VPP Setup VCC Setup Time Chip Enable Setup Time Program Pulse Width Data Hold Time /OE Setup Time Data Access Time Data Output Float Time Over-program Pulse Width EPM Setup Time /PGM Setup Time Address to /OE Setup Time Option Program Pulse Width /OE Low Width Min 2 2 2 2 2 0.95 2 2 188 2.85 2 2 2 150 250 Max Units s s s s s ms s s ns ns ms s s s ms ns
4000 100 3.2
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T2
P01 = Clock
T4 T3 T1
1
P00 = Clear
T5
Internal Address Vih Data Vil Invalid
0 Min
Valid
9
Invalid
Valid
Legend: T1 Reset Clock Width T2 Input Clock High T3 Input Clock Period T4 Input Clock Low T5 Clock to Address Counter Out Delay 30 ns Min 30 ns Min 70 ns Min 30 ns Min 15 ns Max
Figure 19. Z86E02 Address Counter Waveform
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FUNCTIONAL DESCRIPTION (Continued)
VIH Address VIL VIH Data VIL VH VPP VIH VH EPM VIL
12 0 Min
Address Stable
Address Stable
Invalid
9
Valid
Invalid
Valid
VCC
5V VIH
/CE
VIL VIH
0 Min
/OE
VIL
16 16
VIH /PGM VIL
3
Figure 20. Z86E02 Programming Waveform (EPROM Read)
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VIH Address VIL VIH Data VIL VH VIH 6.4V VCC 5V
4 3
1
VPP
/CE /OE
VH VIH
5
VIH VIL
8 8
VIL
VIH EPM VIL VIH /PGM VIL
15 15 12
VIL
12
15
Auto Latch
WDT
ETM Disable
Figure 21. Z86E02 Programming Waveform (Program and Verify)
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FUNCTIONAL DESCRIPTION (Continued)
VIH Address VIL VIH Data VIL VH VPP VIH
3
6.4V VCC 5V
4
VH /CE VIH
5
VIH /OE VIL
VH EPM VIH VIL
12
VIH
12
VIH /PGM VIL
15 15
ROM Protect
Low Noise
Figure 22. Z86E02 Programming Options Waveform (ROM Protect and Low Noise Program)
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VIH Address VIL VIH Data VIL VH VIH 6.4V VCC 5V
4 3
1
VPP
/CE /OE
VH VIH
5
VIH VIL
8 8
VIL
EPM
VIH VIL VIH
VIL
12 12
/PGM
VIL
15 15 15
Auto Latch
WDT
ETM Disable
Figure 23. Z86E02 Programming Options Waveform (Auto Latch Disable, Permanent WDT Enable, and EPROM/TEST MODE Disable)
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FUNCTIONAL DESCRIPTION (Continued)
Start
Addr = First Location
Vcc = 6.4V Vpp = 13.0V
N=0
Program 1 ms Pulse
Increment N
Yes N = 25 ? No Fail Verify One Byte Pass Prog. One Pulse 3xN ms Duration Fail
Verify Byte Pass
Increment Address
No Last Addr ? Yes Vcc = Vpp = 5.0V
Verify All Bytes Pass Device Passed
Fail
Device Failed
Figure 24. Z86E02 Programming Algorithm
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Z8 CONTROL REGISTERS
R241 TMR D7 D6 D5 D4 D3 D2 D1 D0 Reserved (Must be 0) 0 Disable T0 Count 1 Enable T0 Count 0 No Function 1 Load T 1 0 Disable T 1 Count 1 Enable T 1 Count T IN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable) Reserved (Must be 0.)
R247 P3M D7 D6 D5 D4 D3 D2 D1 D0
1
0 Port 2 Open-Drain 1 Port 2 Push-pull Port 3 Inputs 0 Digital Mode 1 Analog Mode Reserved (Must be 0)
Figure 29. Port 3 Mode Register (F7H: Write Only)
R248 P01M D7 D6 D5 D4 D3 D2 D1 D0
P03-P00 Mode 00 = Output 01 = Input Reserved (Must be 1.) Reserved (Must be 0.)
Figure 25. Timer Mode Register (F1H: Read/Write)
R242 T1 D7 D6 D5 D4 D3 D2 D1 D0
Figure 30. Port 0 and 1 Mode Register (F8H: Write Only)
R249 IPR
T1 Initial Value (When Written) (Range 1-256 Decimal 01-00 HEX) T1 Current Value (When READ)
D7 D6 D5 D4 D3 D2 D1 D0
Figure 26. Counter Timer 1 Register (f2H:Read/Write)
R243 PRE1 D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority 000 Reserved 001 C > A > B 010 A > B > C 011 A > C > B 100 B > C > A 101 C > B > A 110 B > A > C 111 Reserved IRQ1, IRQ4 Priority (Group C) 0 IRQ1 > IRQ4 1 IRQ4 > IRQ1 IRQ0, IRQ2 Priority (Group B) 0 IRQ2 > IRQ0 1 IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 IRQ5 > IRQ3 1 IRQ3 > IRQ5 Reserved (Must be 0.)
Count Mode 0 = T 1 Single Pass 1 = T 1 Modulo N Clock Source 1 = T1 Internal 0 = T 1 External Timing Input (T IN ) Mode Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure 31. Interrupt Priority Register (F9H: Write Only)
Figure 27. Prescaler! Register (F3H: Write Only)
R246 P2M D7 D6 D5 D4 D3 D2 D1 D0
P2 7 - P2 0 I/O Definition 0 Defines Bit as OUTPUT 1 Defines Bit as INPUT
Figure 28. Port 2 Mode Register (F6H: Write Only) DS96DZ80301 (11/96) PRELIMINARY 1-33
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
Z8 CONTROL REGISTERS (Continued)
R250 IRQ D7 D6 D5 D4 D3 D2 D1 D0 IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P32 Input IRQ4 = Reserved IRQ5 = T1 Reserved (Must be 0.) R253 RP D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0.) Register Pointer
Figure 35. Register Pointer FDH: Read/Write)
Figure 32. Interrupt Request Register (FAH: Read/Write)
R255 SPL D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Lower Byte (SP 7 - SP 0 ) R251 IMR D7 D6 D5 D4 D3 D2 D1 D0
Figure 36. Stack Pointer (FFH: Read/Write)
1 Enables IRQ5-IRQ0 (D = IRQ0) 0 Reserved (Must be 0.) 1 Enables Interrupts
Figure 33. Interrupt Mask Register (FBH: Read/Write)
R252 Flags D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1 User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure 34. Flag Register (FCH: Read/Write)
1-34
PRELIMINARY
DS96DZ80301 (11/96)
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
PACKAGE INFORMATION
1
Figure 37. 18-Pin DIP Package Diagram
Figure 38. 18-Pin SOIC Package Diagram
DS96DZ80301 (11/96)
PRELIMINARY
1-35
Z86C02/E02/L02 Low-Cost, 512-Byte ROM Microcontrollers
ORDERING INFORMATION
Standard Temperature 18-Pin DIP Z86E0208PSC Z86L0208PSC Z86C0208PSC Z86E0208PSC1903 18-Pin SOIC Z86E0208SSC Z86L0208SSC Z86C0208SSC Z86E0208SSC1903
Extended Temperature 18-Pin DIP Z86E0208PEC Z86L0208PEC Z86C0208PEC Z86E0208PEC1903 18-Pin SOIC Z86E0208SEC Z86L0208SEC Z86C0208SEC Z86E0208SEC1903
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES Preferred Package
P = Plastic DIP
Speed
08 = 8 MHz
Longer Lead Time
S = SOIC
Environmental
C = Plastic Standard
Preferred Temperature
S = 0C to +70C E = -40C to +105C Example: Z 86E08 08 P S C
is a Z86E08, 08 MHz, DIP, 0 to +70C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
1-36
PRELIMINARY
DS96DZ80301 (11/96)

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